# JTL Engineering

### Signal Integrity Analysis

Signals are physical quantities which behave within agreed limits. As such one can assign a state to them. For example in digital signals a voltage above a Vhigh limit would present a one, and below the Vlow limit a zero. The physical quantity (voltage) should keep its shape/definition when traveling over wires and PCB tracks. Signal integrity analysis investigates the amount of signal distortion.

A distinction can be made between amplitude and phase distortion. Both deteriorate the signal but often only one of them matters. For example analog signals are often defined in the frequency domain, they have a certain power in a frequency band, while the momentary phase, that is the exact phase at time t, is not important. Digital signals are defined in the time-domain where the voltage at the sampling frequency of the clock is important. As such time shifts (phase) are important.

Therefore analog signals deteriorate from amplitude distortion that causes extra frequency components. It is caused by non-linear components, i.e. components for which the electrical properties vary with the applied signal level, for example a pn-junction capacitance. Digital signals deteriorate from both amplitude and phase distortion. A (digital) square wave can be considered as a sum of odd harmonics of the square wave frequency, that is .

To maintain the digital signal shape the ratio of the amplitudes of these harmonics should be constant and the phase shift between the harmonics (the group delay) should be zero.

For an approximate square wave the signal should contain at least the first and third harmonic. The more harmonics the less ringing effects and the steeper the slopes. Hold the mouse over the picture on the right to see the effect of the harmonics, click on it to enlarge.

Often the signal voltage need to drive a load with a certain capacitance. The impedance of the capacitance drops with increasing frequency therefore the amplitude of the signal is more reduced and the phase delay is larger. The higher harmonics suffer more distortion then the lower harmonics. The picture on the right shows a square wave filtered by a pole at a harmonic frequency. This causes a 45 degree phase delay and a drop in amplitude at the frequency of the pole. The higher harmonics are more delayed. When adding these delayed and reduced harmonics the square wave shows a typical RC shape with a slow rising edge.

As the frequency of the harmonics increase the load may often first be approximated by a resistor, next by a capacitor. However for high frequencies it will probably be more complex. This picture therefor only serves to show some (but important) effects of a non-ideal load.

### Coupled RLGC model

To investigate the (digital) signal distortion that a certain physical body (bondwires, PCB tracks, via's etc) causes a 3D EM simulation model can be created that describes the electrical properties like attenuation and phase shift. From the s-parameters a so called RLGC model can be created. This RLGC model is a circuit that can be used in time domain simulators, like SPICE. The model shown left has a row for each of the N (transmission) paths/lines and each of these rows contain M sections. These section contain a series R+L and a G+C to ground. This models the electrical behavior of a single line as a transmission line.

The coupling between the lines is due to a partially joint magnetic field, which is modeled by the coupling of the L in a section with the L's in the same section of another line.

Furthermore the charge in the line will influence the charge in another line, which means that the electric fields of a line is coupled to the other lines. As this effect is less pronounced it is normally sufficient to model it by a coupling capacitor between the line and the neighboring line.

The larger the number of sections in a line the better the time delay of a physical line is approached. For lines up to half a wavelength 1 to 4 sections are often enough to have a sufficient accurate model.

### Example of a Coupled RGLC model of a 32 bits bus

As an example consider the pictures below. An IC contains a 32 bits bus that is routed via bondwires, tracks and vias to the backside of a BGA package. The signal lines consist of a bondwire ranging in length from 0.9 to 1.4 mm, a PCB track ranging from 2 to 2.75 mm and a via of 0.2 mm. The total length varies between 3.1 and 4.6 mm.

An IC package with a 32 bits bus

#### Bottom view package with 32 bits bus

First a 3D simulation was done to get a 64-port s-parameters set, each line having two ports, so this set contains 32 coupled two ports. For each of the two-ports the values for the R, L, G and C were calculated. As the two-port is modelled as a transmission line it is characterized by a characteristic impedance Z0 and a propagation constant γ. Using the telegrapher's equations they can be written as

Z0 = √ (R+jωL)/(G+jωC)

γ = √ (R+jωL)(G+jωC)

Therefore

R = Real(γZ)

L = Imag(γZ)/ω

G = Real(γ/Z)

C = Imag(γ/Z)/ω

In the next step the K-factors for the L's were calculated and the coupling capacitors were determined. In principle all parameters are frequency dependent, but if a transmission line is a good model for the 3D structure the frequency dependency of L, C and K is minimal. Only the R and G will vary significant as function of frequency. And a representative value must be chosen.

Calculated L and C values for a single section in the RLGC model  Calculated R and G values for a single section in the RLGC model  Calculated K-factors The above figures show a nearly frequency independent behavior of the model parameters over frequency, except for the resistance and conductance. This means the model should do good in a time domain simulator. As the conductance value is low a constant value will not significantly detoriate the model behavior.

The resistance is important for the Q of the structure and remains difficult in RLGC models. Best practice is to choose an appropriate value by comparing the s-parameters of the model and the 3D structure.

In this example the coupling capacitance between the lines is low (< 50 fF) and plays no important role. For structures in which this coupling capacitance is important the lines can be stimulated in a common mode and a differential mode and for both modes the RLGC parameters can be calculated, by properly choosing the parameters a single RLGC model can be build for both modes.

### And finally the simulated bits in a time domain simulation

The purpose of the RLGC(k) model was to do accurate time domain simulations. The next two pictures show the response of the RLGC(k) model in a spice simulation and the response of the 3D structure in a field simulator. Calculated is the response to a 1-0 pattern on each odd bit line and a 0-0 pattern on each even bit line. The even bit lines show signal spikes due to the coupling to the odd bit lines. As can be seen there is a good match between the results.

Simulated transient of the 3D model (red) and the RLGC model (green) #### A one-zero on a single line on the bus. Red is the result of the 3D solver, green is the result of the RLGC model in spice. #### A zero-zero on a single line. Red is the 3D solver, green is the RLGC model in spice. The spikes are induced by the 1's in the neighboring lines.

When properly calculated a RLGC(k) model can accurately model the time behavior of IC packages or bus structures. If you want help to model your structure send us an email.